When making an integrated circuit (which may also be referred to as an IC, chip or device), a design layout of the IC is made using, for example, CAD tools. A reticle or mask is then produced for the IC design layout and then photolithography is used to transfer features from the reticle or mask to a die (integrated circuit semiconductor wafer).
Typically, the designer will build an IC layout design by adding and arranging cells, comprising multiple features, to the IC layout design. Once the cells have been arranged paths or tracks that will form the electrical connections on the wafer are defined to link the cells together.
Several IC layouts may be arranged together so that a single wafer may be manufactured producing several ICs that may subsequently be separated as required. The ICs will be tested to ensure quality is maintained. The yield is the ratio of the total number of usable ICs produced per wafer to the potential maximum number of ICs per wafer. The yield may be reduced by failures occurring within individual ICs produced from a wafer. There are many reasons why a failure may occur. For instance, if a particular track in an IC layout design is defined to be too thin, i.e. outside of a particular tolerance, a certain percentage of the ICs may be produced with this track broken following variations that may occur within the manufacturing process.
One way to reduce the number of defective ICs on a wafer is to increase the spacing between critical features in the IC layout design. However, this may lead to larger ICs and fewer ICs per wafer, thus lowering the yield even though a greater proportion of ICs actually produced will be usable.
Therefore, there is required a method and apparatus to improve the yield produced when manufacturing ICs.